A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs

Publisher Website

1 April 2005

conference paper
conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/date.2005.44

Abstract

No abstract available

This publication has 1 reference indexed in Scilit:

A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2004

Cited by 55 articles