A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation
- 21 June 2004
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 1, 246-251 Vol.1
- https://doi.org/10.1109/date.2004.1268856
Abstract
This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard cell ASIC or FPGA design flow. The technique combines standard building blocks to make 'new' compound standard cells, which have a close to constant power consumption. Experimental results indicate a 50 times reduction in the power consumption fluctuations.Keywords
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