100-nm n-/p-channel I-MOS using a novel self-aligned structure

Abstract

We have fabricated a 100-nm n-/p-channel I-MOS by adopting a novel structure. The proposed structure shows some advantages over the conventional one in terms of self-alignment and reduced number of photolithography masks. It leads to low fabrication cost, accelerated scaling down, and enhanced performance due to reduced parasitic elements. It shows a normal transistor operation with small subthreshold swing less than 11.8 mV/dec at room temperature. The n- and p-channel I-MOS have an ON/OFF current of 81.1/2.8 and 78.2/3.4 /spl mu/A per /spl mu/m, respectively. The device performance provides a promise for near-ideal switch application.