PBTI/NBTI-Related Variability in TB-SOI and DG MOSFETs
- 22 March 2010
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 31 (5), 408-410
- https://doi.org/10.1109/led.2010.2043812
Abstract
We study positive bias temperature instability/negative bias temperature instability (PBTI/NBTI)-related aging-dependent statistical variability (SV) in 32-nm thin-body silicon-on-insulator (TB-SOI) and 22-nm double-gate (DG) MOSFETs using comprehensive 3-D numerical simulation. Results indicate that a high degree of PBTI/NBTI degradation can introduce a similar level of SV as the variability in the initial ¿virgin¿ devices introduced by random discrete dopants and line edge roughness. Simulations have shown that the TB-SOI and the DG MOSFETs have different susceptibilities to PBTI/NBTI-induced variability.Keywords
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