Evaluation of statistical variability in 32 and 22nm technology generation LSTP MOSFETs

Abstract

The quantitative evaluation of the impact of key sources of static and dynamic statistical variability (SV) are presented for LSTP nMOSFETs corresponding to 32 nm and 22 nm technology generation transistors with thin-body (TB) SOI and double gate (DG) architectures, respectively. The simulation results indicate that TB SOI and DG devices are not only more resistant to random dopant induced variability compared to their bulk counterparts, but are also more tolerant to line edge roughness induced variability. However, the improved static SV performance shifts the emphasis to dynamic SV introduced by trapped charge associated with aging processes.