Enhanced split-architecture - ADC
- 1 January 2006
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 42 (13), 737-739
- https://doi.org/10.1049/el:20061218
Abstract
A split Δ-Σ ADC topology is proposed which provides enhanced noise shaping by cross-coupling the quantisation errors of the two halves of the structure. Unlike the multi-stage noise shaping architecture, the new structure is insensitive to mismatch errors and it does not reduce the stability of the loops. Simulations confirm the effectiveness of the proposed scheme.Keywords
This publication has 3 references indexed in Scilit:
- "Split ADC" architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADCIEEE Journal of Solid-State Circuits, 2005
- A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDRIEEE Journal of Solid-State Circuits, 2005
- Wideband low-distortion delta-sigma ADC topologyElectronics Letters, 2001