Temperature effects of Si interface passivation layer deposition on high-k III-V metal-oxide-semiconductor characteristics

Abstract

In this work, we studied the electrical characteristics of Ta N ∕ Hf O 2 ∕ Ga As metal-oxide-semiconductor capacitors with Si interfacepassivation layer (IPL) under various postdeposition anneal(PDA) conditions and various Si deposition temperatures/times. Using optimal Si IPL under reasonable PDA, post metal anneal conditions, and various Si deposition temperatures, excellent electrical characteristics with low frequency dispersion ( < 5 % , and 50 mV ) and reasonable D it value ( ∼ 10 12 eV − 1 cm − 2 ) can be obtained. It was found that higher temperature of Si IPL deposition and longer PDA time at 600 ° C improved equivalent oxide thickness and leakage current.