Metal gate-HfO/sub 2/ MOS structures on GaAs substrate with and without Si interlayer
- 27 February 2006
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 27 (3), 145-147
- https://doi.org/10.1109/led.2006.870243
Abstract
In this letter, we studied the effects of post-deposition anneal (PDA) time and Si interface control layer (ICL) on the electrical characteristics of the MOS capacitor with high-/spl kappa/ (HfO/sub 2/) material on GaAs. Thin equivalent oxide thickness (EOT<3 nm) with excellent capacitance-voltage (C-V) characteristics has been obtained. The thickness of the Si ICL and PDA time were correlated with C-V characteristics. It was found that high temperature Si ICL deposition and longer PDA time at 600/spl deg/C improved the C-V shape, leakage current, and especially frequency dispersion (<5%).Keywords
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