A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques
- 24 February 2009
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 44 (3), 824-834
- https://doi.org/10.1109/jssc.2008.2012363
Abstract
Digital implementation of analog functions is becoming attractive in CMOS ICs, given the low supply voltage of ultra-scaled processes. Particularly, all-digital PLLs are being considered for RF frequency synthesis. However, they suffer from intrinsic deficiencies making them inferior to traditional analog solutions. The investigation in this paper shows that in-band output spurs, the major shortcoming of wideband divider-less ADPLLs with respect to analog fractional PLLs, are intrinsic and due to the finite resolution of the time-to-digital converter (TDC), even assuming perfect quantization and linearity. Moreover, even if the conceptual spur level is arbitrarily reduced by increasing the TDC resolution, TDC nonlinearities can cause a significant spur re-growth. This paper proposes two techniques to reduce the gap between all-digital and analog implementations of wideband fractional PLLs. These techniques have been applied to a 3 GHz ADPLL, whose bandwidth is programmable from 300 kHz to 1.8 MHz, operating from a 25 MHz reference signal. The test chip features more than 10 dB of worst in-band spur reduction when both corrections are active, for a worst-case in-band spur of -45 dBc at a bandwidth of 1.8 MHz and an in-band noise floor of -101 dBc/Hz. The chip core occupies 0.4 mm2 in 65 nm CMOS technology, and consumes less than 10 mW from a 1.2 V supply.Keywords
This publication has 13 references indexed in Scilit:
- A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter PerformanceIEEE Journal of Solid-State Circuits, 2008
- A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop AnalogyIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2007
- Statistical Linearity Calibration of Time-To-Digital Converters Using a Free-Running Ring OscillatorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- 1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOSIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2006
- Requirements for Time-to-Digital Converters in the context of digital-PLL based Frequency Synthesis and GSM ModulationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phonesIEEE Journal of Solid-State Circuits, 2005
- TDC-based frequency synthesizer for wireless applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- A 700-kHz bandwidth /spl Sigma//spl Delta/ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applicationsIEEE Journal of Solid-State Circuits, 2004
- A high-resolution CMOS time-to-digital converter utilizing a Vernier delay lineIEEE Journal of Solid-State Circuits, 2000
- Full-speed testing of A/D convertersIEEE Journal of Solid-State Circuits, 1984