A spanning tree carry lookahead adder
- 1 January 1992
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 41 (8), 931-939
- https://doi.org/10.1109/12.156535
Abstract
No abstract availableThis publication has 11 references indexed in Scilit:
- Approaching a nanosecond: a 32 bit adderPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- The redundant cell adderPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Delay optimization of carry-skip adders and block carry-lookahead addersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Analysis and design of CMOS Manchester adders with variable carry-skipIEEE Transactions on Computers, 1990
- Fast area-efficient VLSI addersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987
- A Regular Layout for Parallel AddersIEEE Transactions on Computers, 1982
- High-Speed Binary AdderIBM Journal of Research and Development, 1981
- Carry-Select AdderIRE Transactions on Electronic Computers, 1962
- Skip Techniques for High-Speed Carry-Propagation in Binary Arithmetic UnitsIEEE Transactions on Electronic Computers, 1961
- Conditional-Sum Addition LogicIEEE Transactions on Electronic Computers, 1960