A Regular Layout for Parallel Adders
- 1 March 1982
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-31 (3), 260-264
- https://doi.org/10.1109/tc.1982.1675982
Abstract
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Keywords
This publication has 7 references indexed in Scilit:
- The Area-Time Complexity of Binary MultiplicationJournal of the ACM, 1981
- Parallel Prefix ComputationJournal of the ACM, 1980
- The chip complexity of binary arithmeticPublished by Association for Computing Machinery (ACM) ,1980
- Area-time complexity for VLSIPublished by Association for Computing Machinery (ACM) ,1979
- A Survey of Some Recent Contributions to Computer ArithmeticIEEE Transactions on Computers, 1976
- On the Addition of Binary NumbersIEEE Transactions on Computers, 1970
- On the Time Required to Perform AdditionJournal of the ACM, 1965