A process-tolerant cache architecture for improved yield in nanoscale technologies
- 24 January 2005
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 13 (1), 27-38
- https://doi.org/10.1109/tvlsi.2004.840407
Abstract
Process parameter variations are expected to be significantly high in a sub-50-nm technology regime, which can severely affect the yield, unless very conservative design techniques are employed. The parameter variations are random in nature and are expected to be more pronounced in minimum geometry transistors commonly used in memories such as SRAM. Consequently, a large number of cells in a memory are expected to be faulty due to variations in different process parameters. We analyze the impact of process variation on the different failure mechanisms in SRAM cells. We also propose a process-tolerant cache architecture suitable for high-performance memory. This technique dynamically detects and replaces faulty cells by dynamically resizing the cache. It surpasses all the contemporary fault tolerant schemes such as row/column redundancy and error-correcting code (ECC) in handling failures due to process variation. Experimental results on a 64-K direct map L1 cache show that the proposed technique can achieve 94% yield compared to its original 33% yield (standard cache) in a 45-nm predictive technology under /spl sigma//sub Vt-inter/=/spl sigma//sub Vt-intra/=30 mV.Keywords
This publication has 15 references indexed in Scilit:
- Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithmPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Pipeline gating: speculation control for energy reductionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Redundancy techniques for high-density DRAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An efficient BIST method for testing of embedded SRAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A design for high-speed low-power CMOS fully parallel content-addressable memory macrosIEEE Journal of Solid-State Circuits, 2001
- The impact of intrinsic device fluctuations on CMOS SRAM cell stabilityIEEE Journal of Solid-State Circuits, 2001
- Defect tolerance in VLSI circuits: techniques and yield analysisProceedings of the IEEE, 1998
- Design of a fault-tolerant three-dimensional dynamic random-access memory with on-chip error-correcting circuitIEEE Transactions on Computers, 1993
- An analytical access time model for on-chip cache memoriesIEEE Journal of Solid-State Circuits, 1992
- Multiple word/bit line redundancy for semiconductor memoriesIEEE Journal of Solid-State Circuits, 1978