The role of radiation effects in SOI technology development
- 1 October 2014
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
- No. 1078621X,p. 1-2
- https://doi.org/10.1109/s3s.2014.7028233
Abstract
The technical development of radiation resistant CMOS/SOI technologies is reviewed. Inherent hardness of SOI to dose rate upset and latchup has leveraged major developments of SOI technologies. TID hardness for up to the 150nm node was addressed by process hardening. Inherent hardness of 45nm and 32nm technologies reduced the need for TID hardening. As technology is scaled to 28nm and 14nm nodes TID hardening is again required. SEU hardening is addressed by circuit design for a wide range of technologies with significant SEU improvement for 28nm and 14nm is observed.Keywords
This publication has 2 references indexed in Scilit:
- Radiation effects in SOI technologiesIEEE Transactions on Nuclear Science, 2003
- Radiation-Hard CMOS/SOS Standard Cell CircuitsIEEE Transactions on Nuclear Science, 1976