Low-voltage green transistor using ultra shallow junction and hetero-tunneling
- 1 May 2008
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A novel hetero-tunnel transistor (HtFET) with a heterostructure and ultra shallow junction parallel to the dielectric interface is proposed for low-voltage (low-power) electronics. Its potential of scaling Vdd down to 0.2 V is examined with quantum mechanical tunneling theory. Data from high-K metal-gate, Si on Ge hetero-tunnel transistor verifies the HtFET concept.Keywords
This publication has 3 references indexed in Scilit:
- Strained-Si–Strained-SiGe Dual-Channel Layer Structure as CMOS Substrate for Single Workfunction Metal-Gate TechnologyIEEE Electron Device Letters, 2004
- Lateral interband tunneling transistor in silicon-on-insulatorApplied Physics Letters, 2004
- Silicon surface tunnel transistorApplied Physics Letters, 1995