Low-power CMOS threshold-logic gate
- 7 December 1995
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 31 (25), 2157-2159
- https://doi.org/10.1049/el:19951471
Abstract
A new implementation of a threshold gate based on a latch-type comparator that does not consume static power is presented. Simulation results indicate high operation speed and low power consumption, which make it very attractive when used as a basic building block in digital design.Keywords
This publication has 4 references indexed in Scilit:
- A 10-b 20-Msample/s low-power CMOS ADCIEEE Journal of Solid-State Circuits, 1995
- Minimizing power consumption in digital CMOS circuitsProceedings of the IEEE, 1995
- Hazard-free edge-triggered D flipflop based on threshold gatesElectronics Letters, 1994
- CMOS threshold gate and networks for order statistic filteringIEEE Transactions on Circuits and Systems I: Regular Papers, 1994