Minimizing power consumption in digital CMOS circuits
- 1 April 1995
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Proceedings of the IEEE
- Vol. 83 (4), 498-523
- https://doi.org/10.1109/5.371964
Abstract
No abstract availableThis publication has 16 references indexed in Scilit:
- Power estimation for high level synthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Optimizing power using transformationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1995
- Precomputation-based sequential logic optimization for low powerIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1994
- Technology decomposition and mapping targeting low power dissipationPublished by Association for Computing Machinery (ACM) ,1993
- Technology mapping for lower powerPublished by Association for Computing Machinery (ACM) ,1993
- Low-power CMOS digital designIEEE Journal of Solid-State Circuits, 1992
- On average power dissipation and random pattern testability of CMOS combinational logic networksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- Power-supply voltage impact on circuit performance for half and lower submicrometer CMOS LSIIEEE Transactions on Electron Devices, 1990
- High-speed CMOS circuit techniqueIEEE Journal of Solid-State Circuits, 1989
- Ion-implanted complementary MOS transistors in low-voltage circuitsIEEE Journal of Solid-State Circuits, 1972