Maximizing the Performance of 650-V p-GaN Gate HEMTs: Dynamic RON Characterization and Circuit Design Considerations

Abstract

The systematic characterization of a 650-V/13-A enhancement-mode GaN power transistor with p-GaN gate is presented. Critical device parameters such as ON-resistance R _ON and threshold voltage V _TH are evaluated under both static and dynamic (i.e., switching) operating conditions. The dynamic R _ON is found to exhibit different dependence on the gate drive voltage V _GS from the static R _ON . While reasonably suppressed at higher V _GS of 5 and 6 V, the degradation in dynamic R _ON is significantly larger at lower V _GS of 3-4 V, which is attributed to the positive shift in V _TH under switching operations. In addition to characterization of discrete devices, a custom-designed double-pulse test circuit with 400-V, 10-A test capability is built to evaluate the transient switching performance of the p-GaN gate power transistors. Optimal gate drive conditions are proposed to: 1) provide sufficient gate over-drive to minimize the impact of the V _TH shift on the dynamic R _ON ; and 2) leave enough headroom to save the device from excessive gate stresses. Moreover, gate drive circuit design and board layout considerations are also discussed by taking into account the fast switching characteristics of GaN devices.