Enhancement-mode GaN-on-Si MOS-FET using Au-free Si process and its operation in PFC system with high-efficiency
- 1 May 2015
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
We have developed an enhancement-mode GaN-on-Si MOS-FET with a thin GaN channel (40nm) on a thick AlGaN back barrier layer (1um), using Au-free 150-mm Si process. The developed device showed a threshold voltage Vt of 1.1 V, an on-resistance Ron of 5.4 mΩcm2 and a breakdown voltage BV of 730 V. The developed E-mode GaN MOS-FETs demonstrated the potential for compact and efficient power electronics. A Power Factor Correction (PFC) circuit using the packaged GaN device (20A, 650V) operated with high efficiency of > 94 % at Pout=300 W, Vout=390 V and f SW =300 kHz.Keywords
This publication has 6 references indexed in Scilit:
- Normally-OFF Al2O3/AlGaN/GaN MOS-HEMT on 8 in. Si with Low Leakage Current and High Breakdown Voltage (825 V)Applied Physics Express, 2014
- Performance and robustness of first generation 600-V GaN-on-Si power transistorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2013
- High-Performance Normally-Off ${\rm Al}_{2}{\rm O}_{3}/{\rm GaN}$ MOSFET Using a Wet Etching-Based Gate Recess TechniqueIEEE Electron Device Letters, 2013
- Package Parasitic Inductance Extraction and Simulation Model Development for the High-Voltage Cascode GaN HEMTIEEE Transactions on Power Electronics, 2013
- Au-free CMOS-compatible AlGaN/GaN HEMT processing on 200 mm Si substratesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2012
- Recent Advances in GaN Power Switching DevicesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2010