BSM 7: RIE lag in high aspect ratio trench etching of silicon
- 28 February 1997
- journal article
- Published by Elsevier BV in Microelectronic Engineering
- Vol. 35 (1-4), 45-50
- https://doi.org/10.1016/s0167-9317(96)00142-6
Abstract
No abstract availableKeywords
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