A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS

Abstract

From 90 nm and below, SoC integration is reaching the point where it makes technical and economic sense to integrate embedded DRAM (eDRAM) onto a die. While eDRAMs have 2.5x to 4x density compared to SRAMs and have lower soft-error rate they are slower in operation. In a conventional DRAM with a single column access device for read and write, a write operation is started only after the bitline sense amplifiers are turned on and the bitlines are well on their way to full restoration. This is to avoid destroying data due to premature access to global bitlines in the non-writing columns. This delay in the write operation increases row cycle time to allow the storage node to be fully written. Accelerating write cycle with early access only in the required columns requires a large area penalty because local sense amplifiers in one bank are usually grouped into a large block where all control signals are shared. Also an embedded DRAM in a standard 65 nm twin-tub SOI CMOS process that uses a local sense amplifier with V_DD sensing and separate ports for read and write, with these operations synchronized with sensing is described. This eDRAM speeds up the row cycle with low area overhead by reducing the number of signals to control the ports and making write and read operations indistinguishable at the bank level.