A high density memory for SoC with a 143MHz SRAM interface using sense-synchronized-read/write

Abstract

A high density memory (HDRAM) for SoC with SRAM interface is described. This macro achieves no-wait fast random-cycle operation owing to a sense-synchronized read/write scheme. A 4Mb test device is fabricated in a 0.15/spl mu/m process and achieves 143MHz operation. Its size and standby power are 4.59mm/sup 2/ and 92mW, which are 30% and 4.8%, respectively, of an embedded SRAM macro fabricated identically.