Parallel counter implementation
- 1 October 1994
- journal article
- research article
- Published by Springer Science and Business Media LLC in Journal of Signal Processing Systems
- Vol. 7 (3), 223-232
- https://doi.org/10.1007/bf02409399
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
- Digital neural network implementationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- Parallel CountersIEEE Transactions on Computers, 1973
- Multiple Addition by Residue Threshold Functions and Their Representation by Array LogicIEEE Transactions on Computers, 1973
- The Quasi-Serial MultiplierIEEE Transactions on Computers, 1973
- Adder With Distributed ControlIEEE Transactions on Computers, 1970