Mechanism of Electron Trapping and Characteristics of Traps in $\hbox{HfO}_{2}$ Gate Stacks
- 16 July 2007
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Device and Materials Reliability
- Vol. 7 (1), 138-145
- https://doi.org/10.1109/tdmr.2007.897532
Abstract
Electron trapping in high- gate dielectrics under constant voltage stress is investigated. It is suggested that the electron trapping occurs through a two-step process: resonant tunneling of the injected electron into the preexisting defects (fast trapping) and thermally activated migration of trapped electrons to unoccupied traps (slow trapping). Characteristics of the electron traps extracted based on the proposed model are in good agreement with the calculated properties of the negatively charged oxygen vacancies. The model successfully describes low-temperature threshold voltage instability in NMOS transistors with /TiN gate stacks.Keywords
This publication has 14 references indexed in Scilit:
- Ab initio modeling of electron‐phonon coupling in high‐k dielectricsphysica status solidi (c), 2006
- Polaron-like Charge Trapping in Oxygen Deficient and Disordered HfO2: Theoretical InsightECS Transactions, 2006
- Negative oxygen vacancies in HfO2 as charge traps in high-k stacksApplied Physics Letters, 2006
- Mobility evaluation in transistors with charge-trapping gate dielectricsApplied Physics Letters, 2005
- Review on high-k dielectrics reliability issuesIEEE Transactions on Device and Materials Reliability, 2005
- Threshold voltage instabilities in high-/spl kappa/ gate dielectric stacksIEEE Transactions on Device and Materials Reliability, 2005
- Characterization and modeling of hysteresis phenomena in high K dielectricsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Trapping/De-Trapping Gate Bias Dependence of Hf-Silicate Dielectrics with Poly and TiN Gate ElectrodeJapanese Journal of Applied Physics, 2005
- Characterization of Vt instability in hafnium based dielectrics by pulse gate voltage techniques [CMOS device applications]Published by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- Effect of Pre-Existing Defects on Reliability Assessment of High-K Gate DielectricsMicroelectronics Reliability, 2004