Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement
- 8 June 2008
- conference paper
- conference paper
- Published by Association for Computing Machinery (ACM)
- p. 554-559
- https://doi.org/10.1145/1391469.1391610
Abstract
Magnetic random access memory (MRAM) has been considered as a promising memory technology due to many attractive properties. Integrating MRAM with CMOS logic may incur extra manufacture cost, due to its hybrid magnetic-CMOS fabrication process. Stacking MRAM on top of CMOS logics using 3D integration is a way to minimize this cost overhead. In this paper, we discuss the circuit design issues for MRAM, and present the MRAM cache model. Based on the model, we compare MRAM against SRAM and DRAM in terms of area, performance, and energy. Finally we conduct architectural evaluation for 3D microprocessor stacking with MRAM. The experimental results show that MRAM stacking offers competitive IPC performance with a large reduction in power consumption compared to SRAM and DRAM counterparts.Keywords
This publication has 8 references indexed in Scilit:
- Die Stacking (3D) MicroarchitecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- Macro-model of Spin-Transfer Torque based Magnetic Tunnel Junction device for hybrid Magnetic-CMOS designPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- Design space exploration for 3D architecturesACM Journal on Emerging Technologies in Computing Systems, 2006
- A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchyPublished by Association for Computing Machinery (ACM) ,2006
- Design considerations for MRAMIBM Journal of Research and Development, 2006
- Bridging the Processor-Memory Performance Gapwith 3D IC TechnologyIEEE Design & Test of Computers, 2005
- Memories of tomorrowIEEE Circuits and Devices Magazine, 2002
- The SimpleScalar tool set, version 2.0ACM SIGARCH Computer Architecture News, 1997