Software Verification for System on a Chip using a C/C++ Simulator and FPGA Emulator

Abstract

System-on-a-chip (SoC) refers to a system designed by integrating IP (intellectual property) cores such as CPUs, DSPs, and various types of function. Recently, since a complex SoC has more than 10 CPU cores, the software development term of such complex SoCs is longer than the hardware development term of them. Thus, a fast, low cost and accurate simulator for the embedded software for SoC, is needed. In this paper we described a new hardware/software co-verification method for system-on-a-chip, based on the integration of a C/C++ simulator and an inexpensive FPGA emulator. Communication between the simulator and emulator occurs via a flexible interface based on shared communication registers. This method enables easy debugging, rich portability, keeping the clock synchronization, and high verification speed, at a low cost. We applied this environment to the verification of three different complex commercial SoCs, supporting concurrent hardware and embedded software development In these projects, our verification methodology was used to perform complete system verification at 0.2-2.5 MHz, while supporting full graphical interface functions such as "waveform" or "signal dump" viewers, and debugging functions such as "step" or "break". These results indicate that the proposed environment has the adequate performance as the simulator for the embedded software development for SoC