Analysis and Evaluation of Multisite Testing for VLSI

Abstract

This paper deals with multisite testing of VLSI chips in a manufacturing environment. Multisite testing is analyzed and evaluated using device-under-test (DUT) parameters (such as yield and average number of faults per DUT) as well as test process features (such as number of channels, fault coverage, and touchdown time for the head). The presence of idle time periods and their impact on the multisite test time is analyzed in depth. Two hybrid testing scenarios which combine built-in self-test (BIST) and automatic test equipment (ATE) are proposed and analytical models are provided to establish the corresponding multisite test time. It is shown that a hybrid approach based on screening chips through a BIST stage improves the performance of multisite test and allows a better utilization of channels in the head of an ATE.