Hybrid multisite testing at manufacturing
- 8 July 2004
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 1, 927-936
- https://doi.org/10.1109/test.2003.1271079
Abstract
No abstract availableKeywords
This publication has 12 references indexed in Scilit:
- Test scheduling for core-based systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Defect-oriented test schedulingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chipPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- New techniques for deterministic test pattern generationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Analysis and minimization of test time in a combined BIST and external test approachPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Test cost minimization for hybrid BISTPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Pseudorandom TestingIEEE Transactions on Computers, 1987
- Fault coverage requirement in production testing of LSI circuitsIEEE Journal of Solid-State Circuits, 1982
- Defect Level as a Function of Fault CoverageIEEE Transactions on Computers, 1981