Effective Logic Synthesis for Threshold Logic Circuit Design
- 8 May 2018
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 38 (5), 926-937
- https://doi.org/10.1109/tcad.2018.2834434
Abstract
This paper presents a novel and effective logic synthesis flow able to identify threshold logic functions during the technology mapping process. It provides more efficient logic covering, exploring also redundant cuts. Moreover, the proposed design flow takes into account different circuit area estimations, such as the sum of input weights and threshold values, the gate fanin and the number of threshold logic gates. As a result, the mapped circuits present a reduction up to 47% and 67% in area and logic depth, respectively, in comparison to the most recent related approaches.Keywords
Funding Information
- Coordenação de Aperfeiçoamento de Pessoal de Nível Superior
- Conselho Nacional de Desenvolvimento Científico e Tecnológico
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