Optimized Circuit Failure Prediction for Aging: Practicality and Promise
Top Cited Papers
- 1 October 2008
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Circuit failure prediction is used to predict occurrences of circuit failures, during system operation, before errors appear in system data and states. This technique is applicable for overcoming major scaled-CMOS reliability challenges posed by aging mechanisms such as Negative-Bias-Temperature-Instability (NBTI). This is possible because of the gradual nature of degradation associated with such aging mechanisms. Circuit failure prediction uses special on-chip circuits called aging sensors. In this paper, we experimentally demonstrate correct functionality and practicality of two flavors of flip-flop designs with built-in aging sensors using 90 nm test chips. We also present an aging-aware timing analysis technique to strategically place such flip-flops with built-in aging sensors at selective locations inside a chip for effective circuit failure prediction. This aging-aware timing analysis approach also minimizes the chip-level area impact of such aging sensors. Results from two 90 nm designs demonstrate the practicality and effectiveness of optimized circuit failure prediction with overall chip-level area impact of 2.5% and 0.6%.Keywords
This publication has 12 references indexed in Scilit:
- Circuit failure prediction for robust system design in scaled CMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2008
- CASPPublished by Association for Computing Machinery (ACM) ,2008
- Globally Optimized Robust Systems to Overcome Scaled CMOS Reliability ChallengesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2008
- Circuit Failure Prediction and Its Application to Transistor Aging26th IEEE VLSI Test Symposium (vts 2008), 2007
- New characterization and modeling approach for NBTI degradation from transistor to product levelPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2007
- The impact of NBTI on the performance of combinational and sequential circuitsProceedings of the 39th conference on Design automation - DAC '02, 2007
- Predictive Modeling of the NBTI Effect for Reliable DesignPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- Electronics beyond nano-scale CMOSProceedings of the 39th conference on Design automation - DAC '02, 2006
- NBTI degradation: From physical mechanisms to modellingMicroelectronics Reliability, 2006
- Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturingJournal of Applied Physics, 2003