Effects of grain boundaries on the channel conductance of SOl MOSFET's
- 1 August 1983
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 30 (8), 933-940
- https://doi.org/10.1109/t-ed.1983.21240
Abstract
A physical model that describes the effects of grain boundaries on the linear-region (strong-inversion) channel conductance of SOI (polysilicon on silicon-dioxide) MOSFET's is developed and supported experimentally. The model predicts an effective turn-on characteristic that occurs beyond the strong-inversion threshold, and henceforth defines the "carrier mobility threshold voltage" and the effective field-effect carrier mobility in the channel, which typically is higher than the actual (intragrain) mobility. These parameters, which are defined by the properties of the grain boundaries, can easily be misinterpreted experimentally as the threshold voltage and the actual carrier mobility.Keywords
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