Fault indulgent in embedded memory using WCET real-time embedded system
- 1 February 2014
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in International Conference on Information Communication and Embedded Systems (ICICES2014)
Abstract
The growing density of integration and the increasing percentage of system-on-chip memory occupied by embedded programs have led to an increase in the expected amount of power consumption. In order to reduce the integrity and iterations of the embedded programs the WCET has been implemented. By monitoring the Worst Case Execution time we can reduce the clock cycles required by each instruction of the program, which analogously increases the memory consumption based on both RAM and ROM memory in the embedded system and also power consumption criteria. In this paper, a compiler level optimization, namely WCET-aware rescheduling register allocation, is proposed to achieve WCET minimization for realtime embedded systems. The novelty of the proposed approach is that the effects of register allocation, instruction scheduling, and cluster assignment on the quality of generated code are taken into account for WCET minimization. Three compilation processes are integrated into a single phase balanced result obtained with 6kbytes of ROM reduction from 8kbytes.Keywords
This publication has 12 references indexed in Scilit:
- Fault-Tolerant Embedded-Memory Strategy for Baseband Signal Processing SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012
- Minimizing WCET for Real-Time Embedded Systems via Static Instruction Cache LockingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2009
- Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparisonPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2007
- A generalized algorithm for graph-coloring register allocationPublished by Association for Computing Machinery (ACM) ,2004
- Embedded memory test and repair: infrastructure IP for SOC yieldPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- CARS: a new code generation framework for clustered ILP processorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Instruction scheduling for clustered VLIW DSPsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Cluster assignment for high-performance embedded VLIW processorsACM Transactions on Design Automation of Electronic Systems, 2002
- Linear scan register allocationACM Transactions on Programming Languages and Systems, 1999
- Optimal and Near‐optimal Global Register Allocation Using 0-1 Integer ProgrammingSoftware: Practice and Experience, 1996