Dependable design technique for system-on-chip
- 30 April 2008
- journal article
- Published by Elsevier BV in Journal of Systems Architecture
- Vol. 54 (3-4), 452-464
- https://doi.org/10.1016/j.sysarc.2007.09.003
Abstract
No abstract availableKeywords
This publication has 12 references indexed in Scilit:
- Autonomous-repair cell for fault tolerant dynamic-reconfigurable devicesPublished by Association for Computing Machinery (ACM) ,2006
- Dependability computations for fault-tolerant system based on FPGAPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Designing fault-tolerant techniques for SRAM-based FPGAsIEEE Design & Test of Computers, 2004
- Reconfigurable architecture for autonomous self-repairIEEE Design & Test of Computers, 2004
- Designing fault tolerant systems into SRAM-based FPGAsPublished by Association for Computing Machinery (ACM) ,2003
- Common-mode failures in redundant VLSI systems: a surveyIEEE Transactions on Reliability, 2000
- Fault analysis for networks with concurrent error detectionIEEE Design & Test of Computers, 1998
- Logic synthesis of multilevel circuits with concurrent error detectionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1997
- Single event upset at ground levelIEEE Transactions on Nuclear Science, 1996
- Self-checking design in Eastern EuropeIEEE Design & Test of Computers, 1996