A 10-Bit 800-MHz 19-mW CMOS ADC

Abstract

A pipelined ADC employs charge-steering op amps to relax the trade-offs among speed, noise, and power consumption. Such op amps afford a fourfold increase in speed and a twofold reduction in noise for a given power consumption and voltage gain. Applying full-rate nonlinearity and gain error calibration, a prototype realized in 65-nm CMOS technology exhibits a Nyquist SNDR of 52.2 dB and draws 19 mW at 800 MHz. The ADC also demonstrates a new histogram-based background calibration technique.