CACTI: an enhanced cache access and cycle time model
- 1 May 1996
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 31 (5), 677-688
- https://doi.org/10.1109/4.509850
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
- Tradeoffs in two-level on-chip cachingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An analytical access time model for on-chip cache memoriesIEEE Journal of Solid-State Circuits, 1992
- An area model for on-chip memories and its applicationIEEE Journal of Solid-State Circuits, 1991
- A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architectureIEEE Journal of Solid-State Circuits, 1991
- Signal Delay in RC Tree NetworksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983