A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture
- 1 January 1991
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 26 (11), 1577-1585
- https://doi.org/10.1109/4.98975
Abstract
No abstract availableKeywords
This publication has 10 references indexed in Scilit:
- A 128k 6.5 ns access/5 ns cycle CMOS ECL static RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 512 kb/5 ns BiCMOS RAM with 1 kG/150 ps logic gate arrayPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 2ns Cycle, 4ns Access 512kb CMOS ECL SRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- A 5 ns 1 Mb ECL BiCMOS SRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- A 3.5 ns, 2 K×9 self timed SRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- A 3.5 ns/77 K and 6.2 ns/300 K 64 K CMOS RAM with ECL interfacesIEEE Journal of Solid-State Circuits, 1989
- Fast CMOS ECL receivers with 100-mV worst-case sensitivityIEEE Journal of Solid-State Circuits, 1988
- A 32b VLSI systemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- Maximum-rate pipeline systemsPublished by Association for Computing Machinery (ACM) ,1969
- The IBM System/360 Model 91: Floating-Point Execution UnitIBM Journal of Research and Development, 1967