Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits

Abstract

As the number of transistors integrated on a circuit continues to increase, roughly doubling every 18 months, the impact of transistor variations on circuit performance becomes more significant. Even in the absence of systematic variations (implant nonuniformities, Leff and Weff variations), there exists a fundamental variability in the threshold voltage V/sub T/ due to the finite number of dopant atoms in the extremely small MOSFET channel area. This work presents for the first time the impact of these fundamental V/sub T/ variations on SRAM cell stability and CMOS logic performance. We also analyze the impact of device scaling on these V/sub T/ variations and propose guidelines for future SRAM cell design.<>