Abstract
A new BIST TPG design, called low-transition random TPG (LT-RTPG), that is comprised of an LFSR,a k-input AND gate, and a T flip-flop, is presented.When used to generate test patterns for test-per-scanBIST, it decreases the number of transitions that occur during scan shifting and hence decreases the heatdissipated during testing. Various properties of LT-RTPG's are studied and a methodology for their designis presented. Experimental results demonstrate thatLT-RTPG's designed using the proposed methodologydecrease the heat dissipated during BIST by significantamounts while attaining high fault coverage, especiallyfor circuits with moderate to large number of scan inputs.

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