VLSI implementation of an entropy coder and decoder for advanced TV applications

Abstract

Experimental prototype high-speed entropy coder and decoder chips with parallel architectures are discussed. Two coding techniques, run-length coding and variable-length coding, are implemented in these two chips. Designed in a 1.2- mu m double-metal CMOS technology, the die-size of each chip is about 5 mm*5 mm. Each chip contains about 35 K transistors. Based on the simulation of critical parts, they are expected to meet a speed objective of 52 MHz with margin.