Charge redistribution and noise margins in domino CMOS logic
- 1 August 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems
- Vol. 33 (8), 786-793
- https://doi.org/10.1109/tcs.1986.1085987
Abstract
No abstract availableThis publication has 3 references indexed in Scilit:
- Analysis and design optimization of domino CMOS logic with application to standard cellsIEEE Journal of Solid-State Circuits, 1985
- Cascode voltage switch logic: A differential CMOS logic familyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- High-speed compact circuits with CMOSIEEE Journal of Solid-State Circuits, 1982