Comparison of current flash EEPROM erasing methods: stability and how to control
- 1 January 1992
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Digest. International Electron Devices Meeting,
- p. 595-598
- https://doi.org/10.1109/iedm.1992.307431
Abstract
The effects of process and device parameter fluctuations of flash EEPROM cells on the flash-erasing instabilities are systematically investigated using a simple analytical model and numerical simulation. Among various erase methods, the High voltage Source with grounded Erase (HSE) method is the most stable scheme for the control of erasing speed and erased threshold voltage distribution. The stability of HSE is caused by the reduced electric field fluctuations associated with cell parameter variations, due to the source bias effect, especially at the final stage of erasing. It is also found that the recently proposed self-convergence scheme is an effective tool for suppressing the erased-V/sub t/ distribution width, and that negative gate erase designs equipped with this method will be a powerful vehicle for the next generation scaled flash devices.Keywords
This publication has 3 references indexed in Scilit:
- A 5 volt only 16M bit flash EEPROM cell with a simple stacked gate structurePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 5V Only 16Mbit Flash EEPROM Cell Using Highly Reliable Write/Erase TechnologiesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- An In-system Reprogrammable 256k Cmos Flash MemoryPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988