Efficient VLSI-realizable decimators for sigma-delta analog-to-digital converters

Abstract

The authors introduce a class of efficient linear-phase FIR (finite impulse response) decimators for attenuating the out-of-band noise generated by a sigma-delta modulator. These decimators contain no general multipliers and very few data memory locations, thereby making them easily realizable in CMOS VLSI. This is achieved by using several decimation stages, with each stage containing a small number of delays and arithmetic operations. The output sampling rate of these decimators is the minimum possible one, and the proposed decimators can be used, with very slight changes, for many oversampling ratios. Furthermore, these decimators highly attenuate the undesired out-of-band signal components of the input signal, thus significantly relaxing the antialiasing prefilter requirements.