CMOS implementation comparison of NCL gates
- 1 August 2012
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Various CMOS implementations of asynchronous NULL Convention Logic (NCL) gates have been compared in terms of area, speed, energy, power, supply voltage, and noise. Additionally, a new approach to design semi-static NCL gates has been introduced. Each gate type is used to realize a delay-insensitive 4×4 NCL multiplier and the simulation results are compared. It is shown that different realizations excel in different design parameters. This paper aims to provide NCL designers with the tradeoffs of using various NCL gate types.Keywords
This publication has 7 references indexed in Scilit:
- Near-threshold 40nm Supply Feedback C-elementPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2011
- A differential design for C-elements and NCL gatesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2010
- Designing Asynchronous Circuits using NULL Convention Logic (NCL)Published by Springer Science and Business Media LLC ,2009
- NULL Convention Logic/sup TM/: a complete and consistent logic for asynchronous digital circuit synthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- CMOS circuit design of threshold gates with hysteresisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Optimizing CMOS implementations of the C-elementPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Modeling and comparing CMOS implementations of the C-elementIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1998