Parameterized Posit Arithmetic Hardware Generator

Abstract

Hardware implementation of Floating Point Units (FPUs) has been a key area of research due to their massive area and energy footprints. Recently, a proposal was made to replace IEEE 754-2008 technical standard compliant FPUs with Posit Arithmetic Units (PAUs) due to the greater accuracy, speed, and simpler hardware design. In this paper, we present the architecture of a parameterized PAU generator that can generate PAU adders and PAU multipliers of any bit -width pre -synthesis. We synthesize generated arithmetic units using the parameterized PAU generator for 8 -bit, 16 -bit, and 32 -bit adders and multipliers and compare them with IEEE 754-2008 compliant adders and multipliers. Both, synthesis for Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) are performed. In our comparison of m -bit PAU units with n -bit IEEE 754-2008 compliant units, it is observed that the area and energy of a PAU adder and multiplier are comparable to their IEEE 754-2008 compliant counterparts where m= n. We argue that an n -bit IEEE 754-2008 adder and multiplier can be safely replaced with an m -bit PAU adder and multiplier where m<; n, due to superior numerical accuracy of the PAU; we also compare m -bit PAU adders and multipliers with n -bit IEEE 754-2008 compliant adders and multipliers. As an application example, we examine performance in the domain of signal processing with and without PAU adders and multipliers, and show the advantage of our approach.