A 15 ns 32×32-bit CMOS multiplier with an improved parallel structure
- 1 January 1989
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 2 references indexed in Scilit:
- A Suggestion for a Fast MultiplierIEEE Transactions on Electronic Computers, 1964
- A SIGNED BINARY MULTIPLICATION TECHNIQUEThe Quarterly Journal of Mechanics and Applied Mathematics, 1951