A low-power CDR using dynamic CML latches and V/I converter merged with XOR for half-rate linear phase detection
- 1 January 2014
- journal article
- Published by Institute of Electronics, Information and Communications Engineers (IEICE) in IEICE Electronics Express
- Vol. 11 (17), 20140657
- https://doi.org/10.1587/elex.11.20140657
Abstract
No abstract availableThis publication has 3 references indexed in Scilit:
- A 25-Gb/s 5-mW CMOS CDR/DeserializerIEEE Journal of Solid-State Circuits, 2013
- Loop latency reduction technique for all-digital clock and data recovery circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2009
- A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detectorIEEE Journal of Solid-State Circuits, 2001