Design for Testability of Sleep Convention Logic
- 24 April 2015
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 24 (2), 743-753
- https://doi.org/10.1109/tvlsi.2015.2419816
Abstract
Testability is a major concern in industry for today's complex system-on-chip design. Design-for-testability (DFT) techniques are essential for any logic style, including asynchronous logic styles in order to reduce the test cost. Sleep convention logic (SCL) is a new promising asynchronous logic style that is based on the more well-known asynchronous logic style NULL convention logic (NCL). In contrast to the NCL, there are currently no design for testability methodologies existing for the SCL. The aim of this paper is to analyze the various faults within SCL pipelines and propose a scan-based DFT methodology to make the SCL testable. The proposed DFT methodology is then validated through a number of experiments, showing that the methodology provides a high test coverage (>99%). The complete DFT methodology as well as the scan chain and scan cell design are presented.Keywords
This publication has 20 references indexed in Scilit:
- Gate Mapping Automation for Asynchronous NULL Convention Logic CircuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2013
- CMOS Implementation of Threshold Gates with HysteresisIFIP Advances in Information and Communication Technology, 2013
- CMOS implementation comparison of NCL gatesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2012
- Uncle - An RTL Approach to Asynchronous DesignPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2012
- A Designer's Guide to Asynchronous VLSIPublished by Cambridge University Press (CUP) ,2010
- Designing Asynchronous Circuits using NULL Convention Logic (NCL)Published by Springer Science and Business Media LLC ,2009
- Multi-Threshold Asynchronous Circuit Design for Ultra-Low PowerJournal of Low Power Electronics, 2008
- Speedup of self-timed digital systems using Early CompletionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- CMOS circuit design of threshold gates with hysteresisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Delay-insensitive codes — an overviewDistributed Computing, 1988