The improvement of conditional sum adder for low power applications
- 27 November 2002
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
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- Minimizing power consumption in digital CMOS circuitsProceedings of the IEEE, 1995
- Low-Power Digital VLSI DesignPublished by Springer Science and Business Media LLC ,1995
- A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logicIEEE Journal of Solid-State Circuits, 1990