Using a massively parallel architecture for integrated circuits testing

Abstract

The paper describes the application of a prototype of a massively parallel processing machine to the acceleration of a number of tasks in the debugging of Integrated Circuits by the use of Scanning Electron Microscopy. In particular the machine is used in a number of low level image processing tasks taking advantage in some cases of the specific characteristics of the images of the surface of a VLSI integrated circuit. Preliminary results show that, even with the current experimental prototype, the performance figures for these tasks are one order of magnitude better than those of a state of the art workstation.