Neural network based attack on a masked implementation of AES
- 1 May 2015
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)
- p. 106-111
- https://doi.org/10.1109/hst.2015.7140247
Abstract
Masked implementations of cryptographic algorithms are often used in commercial embedded cryptographic devices to increase their resistance to side channel attacks. In this work we show how neural networks can be used to both identify the mask value, and to subsequently identify the secret key value with a single attack trace with high probability. We propose the use of a pre-processing step using principal component analysis (PCA) to significantly increase the success of the attack. We have developed a classifier that can correctly identify the mask for each trace, hence removing the security provided by that mask and reducing the attack to being equivalent to an attack against an unprotected implementation. The attack is performed on the freely available differential power analysis (DPA) contest data set to allow our work to be easily reproducible. We show that neural networks allow for a robust and efficient classification in the context of side-channel attacks.Keywords
This publication has 20 references indexed in Scilit:
- Side-Channel Attacks on the Yubikey 2 One-Time Password GeneratorLecture Notes in Computer Science, 2013
- Improving cross-device attacks using zero-mean unit-variance normalizationJournal of Cryptographic Engineering, 2012
- RSM: A small and fast countermeasure for AES, secure against 1st and 2nd-order zero-offset SCAsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2012
- Using Subspace-Based Template Attacks to Compare and Combine Power and Electromagnetic Information LeakagesLecture Notes in Computer Science, 2008
- Templates vs. Stochastic MethodsLecture Notes in Computer Science, 2006
- Template Attacks in Principal SubspacesLecture Notes in Computer Science, 2006
- A logic level design methodology for a secure DPA resistant ASIC or FPGA implementationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- An Implementation of DES and AES, Secure against Some AttacksLecture Notes in Computer Science, 2001
- Differential Power Analysis in the Presence of Hardware CountermeasuresLecture Notes in Computer Science, 2000
- DES and Differential Power Analysis The “Duplication” MethodLecture Notes in Computer Science, 1999