A computation and energy reduction technique for HEVC Discrete Cosine Transform
- 19 July 2016
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Consumer Electronics
- Vol. 62 (2), 166-174
- https://doi.org/10.1109/tce.2016.7514716
Abstract
In this paper, a novel computation and energy reduction technique for High Efficiency Video Coding (HEVC) Discrete Cosine Transform (DCT) for all Transform Unit (TU) sizes is proposed. The proposed technique reduces the computational complexity of HEVC DCT significantly at the expense of slight decrease in PSNR and slight increase in bit rate by only calculating several pre-determined low frequency coefficients of TUs and assuming that the remaining coefficients are zero. It reduced the execution time of HEVC HM software encoder up to 12.74%, and it reduced the execution time of DCT operations in HEVC HM software encoder up to 37.27%. In this paper, a low energy HEVC 2D DCT hardware for all TU sizes is also designed and implemented using Verilog HDL. The proposed hardware, in the worst case, can process 53 Ultra HD (7680x4320) video frames per second. The proposed technique reduced the energy consumption of this hardware up to 18.9%. Therefore, it can be used in portable consumer electronics products that require a real-time HEVC encoder.Keywords
This publication has 13 references indexed in Scilit:
- High-performance multiplierless DCT architecture for HEVCPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2015
- Hardware architectures for the H.265/HEVC discrete cosine transformIET Image Processing, 2015
- A low energy HEVC inverse transform hardwareIEEE Transactions on Consumer Electronics, 2014
- A computation and energy reduction technique for HEVC intra mode decisionIEEE Transactions on Consumer Electronics, 2014
- A high performance deblocking filter hardware for high efficiency video codingIEEE Transactions on Consumer Electronics, 2013
- Efficient Integer DCT Architectures for HEVCIEEE Transactions on Circuits and Systems for Video Technology, 2013
- A Novel Algorithm for Zero Block Detection in High Efficiency Video CodingIEEE Journal of Selected Topics in Signal Processing, 2013
- Complexity analysis of an HEVC decoder based on a digital signal processorIEEE Transactions on Consumer Electronics, 2013
- Adaptive Method for Early Detecting Zero Quantized DCT Coefficients in H.264/AVC Video EncodingIEEE Transactions on Circuits and Systems for Video Technology, 2008
- An improved early detection algorithm for all-zero blocks in H.264 video encodingIEEE Transactions on Circuits and Systems for Video Technology, 2005